Draft preview. Lessons are being written and reviewed.
SILICON AGESCoursesPracticeExploreStudy planRoadmaps
Labs and more
Verilog practiceLabsProtocolsBug HuntQuizInterview questionsProjects
VideosReels

Verilog practice

Write the module, press Run, and your design is tested in the browser against expected results. When it fails you see the exact cycle, as a waveform. No account and no install. Your progress stays in this browser.

0day streak
Easy0 of 12
Medium0 of 15
Hard0 of 7
Problem of the dayFour gates at once
1Four gates at onceEasyGates22-to-1 multiplexer, 8 bits wideEasyCombinational34-to-1 multiplexerEasyCombinational42-to-4 decoder with enableEasyCombinational5Full adderEasyArithmetic64-bit adder with carryEasyArithmetic7Even parity bitEasyGates8Binary to Gray codeEasyCombinational9D flip-flop with synchronous resetEasySequential108-bit register with enableEasySequential114-bit up counterEasyCounters12Rising-edge detectorEasySequential138-to-3 priority encoderMediumCombinational144-bit magnitude comparatorMediumArithmetic15Small 8-bit ALUMediumArithmetic16Rotate left by any amountMediumCombinational17Count the onesMediumArithmetic18Gray code back to binaryMediumCombinational194 × 4 multiplierMediumArithmetic20Decade counter with enableMediumCounters21Up/down counter with loadMediumCounters22Serial in, parallel outMediumSequential234-bit LFSRMediumSequential24Johnson counterMediumCounters25Tick every fifth cycleMediumCounters26Detect both edgesMediumSequential27Find 101 in a bit streamMediumFSM28Two-bit branch predictorHardFSM29Traffic light controllerHardFSM30Round-robin arbiterHardDesign31PWM generatorHardDesign32Button debouncerHardFSM33Vending machineHardFSM34Sum of the last four samplesHardDesign

Each problem is checked with a hidden test of up to a few hundred cycles. Expected results were made with Icarus Verilog. The checker in your browser supports one module at a time with the common synthesizable subset: no module instances, memories or initial blocks yet.