Projects

Each course has minor projects, major projects and one industry-level project. You alter the design, then explain what changed.

Minor projects4

A few days. One block, built and tested well.

UART transmitter and receiverSerial framing, baud generation, oversampling, loopback test.Digital Design · ready to startSPI controllerAll four clock modes, tested with a behavioural peripheral.Digital Design · ready to startRound-robin arbiterFair grants, proven with a starvation check.Digital Design · ready to startTransistor sizing studySweep W and L on an open PDK and explain the current and delay.Device Physics and Modelling · planned

Major projects7

A few weeks. A complete design with its own tests.

Small RISC-style CPUYour own instruction set, pipelined, running your test program.Digital Design · ready to startAsynchronous FIFOGray pointers, tested across many clock ratios.Digital Design · ready to startStandard cell characterizationDelay and power tables for an inverter across corners.SPICE Simulation · plannedFIFO verification environmentScoreboard, coverage and assertions, shown on the grid.Verification · plannedScan insertion and ATPG studyCoverage results on a small design.Design for Test · plannedCharacterization data analysisBuild shmoo plots and yield reports from supplied original data.Post-Silicon Validation · plannedVideo or sensor pipelineRunning on a low-cost board, with timing closed.FPGA · planned

Industry projects4

Done the way a team ships it: specification, code, checks and a report.

Streaming packet engineSpecification, RTL, testbench, synthesis report, design document.Digital Design · ready to startSRAM bitcell analysisRead margin, write margin and leakage on an open PDK.Custom Layout and Memory · plannedUVM agent for an APB slaveDriver, monitor, scoreboard and a coverage closure report.Verification · plannedRTL to GDS on an open PDKFloorplan to signoff, with a written analysis of every stage.Physical Design · planned