Verilog practice / Problem 31
PWM generator
A free-running 4-bit counter steps 0, 1, … 15, 0, … on each rising edge and resets to 0. pwm is 1 while that counter is less than duty, so a duty of 4 keeps pwm high for 4 cycles out of 16, and a duty of 0 keeps it low.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
duty | input | 4 |
pwm | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Up, down and loadable counters.
pwm4.vCtrl + Enter runs