Verilog practice / Problem 9
D flip-flop with synchronous reset
On every rising edge of clk, q takes the value of d. If rst is 1 at that edge, q becomes 0 instead.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
d | input | 1 |
q | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson The D flip-flop.
dff.vCtrl + Enter runs