Verilog practice / Problem 20
Decade counter with enable
q counts 0, 1, … 9, 0, … but only moves on a clock edge when en is 1. wrap is 1 when en is 1 and q is 9, so it marks the cycle just before the count returns to 0. rst sets q to 0.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
en | input | 1 |
q | output | 4 |
wrap | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Up, down and loadable counters.
mod10.vCtrl + Enter runs