Verilog practice / Problem 1
Four gates at once
Drive four outputs from the two inputs a and b: y_and is a AND b, y_or is a OR b, y_xor is a XOR b, and y_nand is NOT (a AND b).
Ports
| Name | Direction | Bits |
|---|---|---|
a | input | 1 |
b | input | 1 |
y_and | output | 1 |
y_or | output | 1 |
y_xor | output | 1 |
y_nand | output | 1 |
How it's checked
The test tries the input combinations and checks every output for each one.
Stuck? Read the lesson Logic gates and truth tables.
gates.vCtrl + Enter runs