Verilog practice / Problem 7
Even parity bit
A sender adds one parity bit p so that the 9 bits (d plus p) always hold an even number of 1s. Compute p for the 8-bit input d. For example, d = 8'b0000_0111 has three 1s, so p = 1.
Ports
| Name | Direction | Bits |
|---|---|---|
d | input | 8 |
p | output | 1 |
How it's checked
The test tries the input combinations and checks every output for each one.
Stuck? Read the lesson Logic gates and truth tables.
parity8.vCtrl + Enter runs