Verilog practice / Problem 22
Serial in, parallel out
On each rising clock edge, shift din into the bottom of the 8-bit register q; every bit moves up one place and the top bit falls off. After eight clocks, q holds the last eight inputs, with the newest in bit 0. rst clears q.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
din | input | 1 |
q | output | 8 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Shift registers.
sipo8.vCtrl + Enter runs