Verilog practice / Problem 23
4-bit LFSR
Build a linear feedback shift register. Reset loads q = 4'b0001. On every other rising edge, q shifts left by one and the new bit 0 is q[3] XOR q[2]. The pattern visits all 15 non-zero values before it repeats.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
q | output | 4 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson LFSRs.
lfsr4.vCtrl + Enter runs