Verilog practice / Problem 12
Rising-edge detector
rise is 1 in a cycle where sig is 1 but was 0 in the previous cycle. Remember the previous value of sig in a flip-flop at each clock edge. Reset sets that remembered value to 0, so sig starting high counts as a rise.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
sig | input | 1 |
rise | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Edge detectors and pulse generators.
rise_detect.vCtrl + Enter runs