Verilog practice / Problem 14
4-bit magnitude comparator
Compare two unsigned 4-bit numbers. Exactly one output is 1: eq when a = b, gt when a > b, lt when a < b.
Ports
| Name | Direction | Bits |
|---|---|---|
a | input | 4 |
b | input | 4 |
eq | output | 1 |
gt | output | 1 |
lt | output | 1 |
How it's checked
The test tries the input combinations and checks every output for each one.
Stuck? Read the lesson Subtractors, comparators and an ALU.
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