Verilog practice / Problem 29
Traffic light controller
light shows the current colour: 0 for red, 1 for green, 2 for yellow. After reset the light is green. Green lasts 5 cycles, yellow 2 cycles and red 4 cycles, then it goes back to green and repeats. The first cycle after rst goes low is the first green cycle.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
light | output | 2 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Traffic light and vending machine.
traffic.vCtrl + Enter runs