Up/down counter with load

At each rising clock edge, check the controls in this order: rst sets q to 0; else load copies d into q; else if en is 1, q counts up when up is 1 and down when up is 0. The count wraps both ways, so 0 − 1 gives 15.

Ports

How it's checked

Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.

Stuck? Read the lesson Up, down and loadable counters.