Verilog practice / Problem 27
Find 101 in a bit stream
One bit of din arrives on each rising clock edge. detect goes to 1 for one cycle right after the edge that captures the final 1 of the pattern 1, 0, 1. Overlaps count: the stream 1, 0, 1, 0, 1 contains two matches. Reset clears any partial match.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
din | input | 1 |
detect | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Detecting 1101, with overlap.
detect101.vCtrl + Enter runs