Verilog practice / Problem 24
Johnson counter
A 4-bit Johnson counter: on each rising edge, q shifts left by one and the new bit 0 is the inverse of the old bit 3. Starting from 0000 after reset, it steps 0001, 0011, 0111, 1111, 1110, 1100, 1000, 0000 and repeats.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
q | output | 4 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Ring, Johnson and Gray counters.
johnson4.vCtrl + Enter runs