Quiz

Your waveform viewer shows an 8-bit bus at 0x80, and the spec says the bus is signed. What value is on it?

A 5-input XOR has exactly three inputs high. What does it output?

Your library has only 2:1 muxes, and you need a 4:1. How many do you place?

Which addition makes a carry travel through all the bits of an 8-bit ripple adder?

An 8-bit ALU adds 100 + 100. Which flags are set?

A signal is x in simulation, and the code says if (sig) y = 1; else y = 0;. What does simulation give for y?

In a clocked block, a = 2 and b = 9 before the edge, and the code says a <= b; b <= a;. What are they afterwards?

A teammate's combinational block has if (en) y = a; and nothing else. What does synthesis build for y?

A signal passes through three flops in a row, with no logic between them. How long before a change reaches the last output?

Your chip comes back from the fab with a timing failure, and slowing the clock fixes it. What kind of failure was it?

When is an asynchronous reset dangerous?

A 5-bit LFSR has maximal-length taps. How long before its sequence repeats?

You need a 1 kHz tick from a 50 MHz clock. What does the counter count up to, and how wide is it?

You have 5 flops wired as a Johnson counter. How many states does it step through?

In a divide-by-5 clock with a 50% duty cycle, how long is the output high?

A block needs an answer in the same cycle as its input, and you can accept the extra timing path. Which machine fits?

How many flops do 9 states need in binary and in one-hot?

With overlap allowed, how many times does 1101 appear in the stream 1101101101?

Same stream, 1101101101, but now matches can't share bits. How many?

How wide are the pointers in a depth-16 synchronous FIFO using the extra-bit method?

A burst of 200 words arrives at 200 MHz, while the reader runs at 100 MHz. What's the smallest ideal depth?

Over four cycles, valid is 1, 1, 1, 1 and ready is 0, 1, 0, 1. How many words transfer?

Ready passes through one register on its way upstream. How many spare entries keep every word safe?

You multiply a 12-bit value by an 8-bit value. How wide should the result be to keep every bit?

You multiply two Q3.5 numbers. What format is the full product?

A block has 12 ns of logic, split evenly into 4 stages, with 0.5 ns of flop overhead per stage. What's the clock period?

Tcq is 0.2 ns, the logic takes 1.5 ns, and setup is 0.3 ns. With a 1.8 ns clock, what's the setup slack?

The capture clock now arrives 0.3 ns later than the launch clock. What happens to this path?

Late in the flow, the report shows a hold violation between two neighbouring flops. What's the usual fix?

You declare a multicycle setup of 3 on a path launched and captured by one clock. What multicycle hold usually goes with it?

Adding a synchronizer stage gives one more clock period T of settling time. Roughly how does MTBF change?

A one-cycle pulse crosses from 500 MHz to 50 MHz. What's the right approach?

Why is a two-flop synchronizer on each bit of a data bus a bad idea?

What is the binary value 6 (110) in Gray code?

The writer sees a stale read pointer. How can that affect its full flag?

Timing still closes when you drop the supply voltage by 20%. Roughly how much does dynamic power fall?

What does req & (~req + 1) give when req is 0110100?