Tick every fifth cycle

Make a one-cycle pulse every fifth clock. Number the cycles from 1, starting with the first cycle after rst goes low. tick must be 1 in cycles 5, 10, 15 and so on, and 0 in every other cycle.

Ports

How it's checked

Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.

Stuck? Read the lesson Odd division with 50% duty cycle.