Verilog practice / Problem 2
2-to-1 multiplexer, 8 bits wide
When sel is 0, y copies a. When sel is 1, y copies b. All data is 8 bits wide.
Ports
| Name | Direction | Bits |
|---|---|---|
a | input | 8 |
b | input | 8 |
sel | input | 1 |
y | output | 8 |
How it's checked
The test tries the input combinations and checks every output for each one.
Stuck? Read the lesson Multiplexers.
mux2.vCtrl + Enter runs