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Verilog practice / Problem 34

HardDesign

Sum of the last four samples

At each rising edge, capture the 8-bit input x. sum is the total of the four most recent captured values. Slots not yet filled since reset count as 0. The largest total is 4 × 255 = 1020, so sum has 10 bits.

Ports

NameDirectionBits
clkinput1
rstinput1
xinput8
sumoutput10

How it's checked

Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.

Stuck? Read the lesson Pipelining.

sum4.vCtrl + Enter runs