Verilog practice / Problem 26
Detect both edges
chg is 1 in any cycle where sig differs from its value in the previous cycle, whether it went up or down. Keep the previous value in a flip-flop, which reset sets to 0.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
sig | input | 1 |
chg | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Edge detectors and pulse generators.
any_edge.vCtrl + Enter runs