Verilog practice / Problem 30
Round-robin arbiter
Four clients raise bits of req. grant is one-hot: it picks one requesting client in the same cycle, or is 0 when nobody asks. Search starts at the client just after the one granted most recently and wraps around: after client 1, search 2, 3, 0, 1. Remember the most recent grant at each rising edge; after reset, act as if client 3 was granted last, so client 0 comes first.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
req | input | 4 |
grant | output | 4 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Arbiters.
rr_arbiter.vCtrl + Enter runs