Verilog practice / Problem 3
4-to-1 multiplexer
sel picks one of four 4-bit inputs: 0 picks d0, 1 picks d1, 2 picks d2 and 3 picks d3.
Ports
| Name | Direction | Bits |
|---|---|---|
d0 | input | 4 |
d1 | input | 4 |
d2 | input | 4 |
d3 | input | 4 |
sel | input | 2 |
y | output | 4 |
How it's checked
The test tries the input combinations and checks every output for each one.
Stuck? Read the lesson Multiplexers.
mux4.vCtrl + Enter runs