Verilog practice / Problem 11
4-bit up counter
q goes up by one on every rising clock edge and wraps from 15 back to 0. rst sets it to 0.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
q | output | 4 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Up, down and loadable counters.
counter4.vCtrl + Enter runs