Verilog practice / Problem 28
Two-bit branch predictor
A saturating counter from 0 to 3 guesses whether a branch will be taken. Reset sets it to 1. On a rising edge with valid = 1, the counter goes up by one if taken is 1 and down by one if taken is 0, but it never goes past 3 or below 0. The guess predict is 1 when the counter is 2 or 3.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
valid | input | 1 |
taken | input | 1 |
predict | output | 1 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Traffic light and vending machine.
predictor2.vCtrl + Enter runs