Free chip design courses

68lessons

53animations

42bugs to find

37quiz questions

Binary, hex and two's complement Logic gates and truth tables Boolean algebra and De Morgan Karnaugh maps What a gate is made of: CMOS Multiplexers Decoders and priority encoders Half, full and ripple adders Carry look-ahead and prefix adders Subtractors, comparators and an ALU Barrel shifters and glitches Modules, ports and hierarchy wire, reg, logic and 4-state values assign and always blocks Blocking and non-blocking assignments Accidental latches Parameters and generate Your first self-checking testbench Reading waveforms like an engineer SR and D latches The D flip-flop Setup and hold: the two promises Synchronous and asynchronous resets Enables and clock gating Shift registers LFSRs Up, down and loadable counters Ring, Johnson and Gray counters Divide by 2, 4 and any even number Odd division with 50% duty cycle Edge detectors and pulse generators States, transitions and outputs Moore and Mealy machines Writing FSMs: encoding and style Detecting 1101, with overlap Non-overlapping detection Traffic light and vending machine Debugging and safe FSMs Register files Using SRAM in RTL Synchronous FIFO FIFO depth calculation Valid/ready handshakes Skid buffers Multipliers and Booth encoding Fixed-point arithmetic Pipelining Retiming and area-speed trade-offs The timing path Clock skew and jitter Fixing violations Constraints, false and multicycle paths Metastability and MTBF The two-flop synchronizer Pulse crossing fast to slow Multi-bit transfers and handshakes Gray code pointers Asynchronous FIFO Reset synchronizers and RDC What synthesis does to your code Lint and code quality Low-power RTL Arbiters Minor project: UART transmitter and receiver Minor project: SPI controller Major project: small RISC-style CPU Industry project: streaming packet engine Interview patternsBinary, hex and two's complement Logic gates and truth tables Boolean algebra and De Morgan Karnaugh maps What a gate is made of: CMOS Multiplexers Decoders and priority encoders Half, full and ripple adders Carry look-ahead and prefix adders Subtractors, comparators and an ALU Barrel shifters and glitches Modules, ports and hierarchy wire, reg, logic and 4-state values assign and always blocks Blocking and non-blocking assignments Accidental latches Parameters and generate Your first self-checking testbench Reading waveforms like an engineer SR and D latches The D flip-flop Setup and hold: the two promises Synchronous and asynchronous resets Enables and clock gating Shift registers LFSRs Up, down and loadable counters Ring, Johnson and Gray counters Divide by 2, 4 and any even number Odd division with 50% duty cycle Edge detectors and pulse generators States, transitions and outputs Moore and Mealy machines Writing FSMs: encoding and style Detecting 1101, with overlap Non-overlapping detection Traffic light and vending machine Debugging and safe FSMs Register files Using SRAM in RTL Synchronous FIFO FIFO depth calculation Valid/ready handshakes Skid buffers Multipliers and Booth encoding Fixed-point arithmetic Pipelining Retiming and area-speed trade-offs The timing path Clock skew and jitter Fixing violations Constraints, false and multicycle paths Metastability and MTBF The two-flop synchronizer Pulse crossing fast to slow Multi-bit transfers and handshakes Gray code pointers Asynchronous FIFO Reset synchronizers and RDC What synthesis does to your code Lint and code quality Low-power RTL Arbiters Minor project: UART transmitter and receiver Minor project: SPI controller Major project: small RISC-style CPU Industry project: streaming packet engine Interview patterns

A FIFO is a ring. Turn it.

Drag it, change the clocks, and watch the pointers chase each other.

Try one now

Write a state machine and watch it runYour code drives the diagram, and it stops at the exact clock where it goes wrong.Find the bug42 broken designs. Read what goes wrong, find the line, and learn why it fails.Scroll through a protocol, clock by clockAXI, APB, SPI, I2C and UART, with the waveform following you.Have an interview soon?Pick your role and the days left, and get the key concepts in order.

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RTL Design Engineer Verification Engineer Physical Design Engineer DFT Engineer Analog Designer Device Engineer Memory Designer Post-Silicon Validation Engineer FPGA Engineer

All 16 courses

FoundationsPlanned6 topics planned Digital DesignReady to study68 lectures3 minor projects2 major projects1 industry project RTL and SystemVerilogPlanned6 topics planned Device Physics and ModellingPlanned7 topics planned1 minor project SPICE SimulationPlanned8 topics planned1 major project Analog and Mixed SignalPlanned8 topics planned Custom Layout and MemoryPlanned7 topics planned1 industry project Logic Synthesis and STAPlanned7 topics planned VerificationPlanned8 topics planned1 major project1 industry project Design for TestPlanned6 topics planned1 major project Physical DesignPlanned9 topics planned1 industry project Post-Silicon ValidationPlanned7 topics planned1 major project FPGAPlanned6 topics planned1 major project Protocols LibraryPlanned15 topics planned Computer Architecture and AI HardwarePlanned6 topics planned Fabrication, Packaging and CareersPlanned7 topics planned

Learn to build chips by watching your own code run.

A FIFO is a ring. Turn it.

Try one now

Which role do you want?

All 16 courses