Verilog practice / Problem 10
8-bit register with enable
An 8-bit register. At a rising clock edge: if rst is 1, q becomes 0. Otherwise, if en is 1, q loads d. If en is 0, q keeps its value.
Ports
| Name | Direction | Bits |
|---|---|---|
clk | input | 1 |
rst | input | 1 |
en | input | 1 |
d | input | 8 |
q | output | 8 |
How it's checked
Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.
Stuck? Read the lesson Enables and clock gating.
reg_enable.vCtrl + Enter runs