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Verilog practice / Problem 32

HardFSM

Button debouncer

A push button bounces, so din flickers before it settles. dout is the clean version: it starts at 0 after reset and changes only at the 4th rising edge in a row at which din differs from dout. If din goes back to match dout before that, the wait starts over.

Ports

NameDirectionBits
clkinput1
rstinput1
dininput1
doutoutput1

How it's checked

Each cycle: the test sets the inputs, waits for your logic to settle, checks the outputs, then gives one rising clock edge. It holds rst high for the first two cycles and once more later on.

Stuck? Read the lesson Traffic light and vending machine.

debounce.vCtrl + Enter runs