Explore
Everything on the site in one place. Search for a topic, or filter by what you feel like doing.
Verilog practice
34 problems. Write the module, run the tests, see your waveform.
Bug Hunt
42 broken designs. Read what goes wrong, then find the line.
Quiz
37 questions, and each answer explains why.
Labs
Change a value and watch what happens.
Protocols
Click through AXI cycle by cycle.
Study plan
A day-by-day plan for your goal or interview.
Interview questions
Think first, then reveal the answer.
Digital Design, lesson by lesson
68 lectures3 minor projects2 major projects1 industry projectModule 1: Numbers and logic 5 lessons
Module 2: Combinational building blocks 6 lessons
Module 3: Verilog that means hardware 8 lessons
Module 4: Sequential logic 7 lessons
Module 5: Counters and frequency dividers 5 lessons
Module 6: Finite state machines 7 lessons
Module 7: Memories and FIFOs 6 lessons
Module 8: Arithmetic and datapaths 4 lessons
Module 9: Static timing 4 lessons
Module 10: Clock domain crossing 7 lessons
Module 11: Designing for silicon 4 lessons
Module 12: Projects and interview preparation 5 lessons
Other courses, coming later
Foundations Planned6 topics planned
The tools every chip engineer uses daily.
- Linux and the shell
- Git and GitHub
- Tcl
- Python for hardware
- Makefiles
- Circuits refresher
RTL and SystemVerilog Planned6 topics planned
Code that synthesizes the way you intended.
- SystemVerilog for design
- Interfaces and packages
- Lint
- Reset architecture
- CDC methodology
- Low-power intent (UPF)
Device Physics and Modelling Planned7 topics planned1 minor project
See what changing a transistor really does.
- Bands and carriers
- PN junction
- MOSFET operation
- Short-channel effects
- FinFET and GAA
- BSIM models
- Corners and variation
SPICE Simulation Planned8 topics planned1 major project
From a first netlist to Monte Carlo.
- Netlists
- DC and AC analysis
- Transient
- Parametric sweeps
- Corners
- Monte Carlo
- Cell characterization
- Convergence
Analog and Mixed Signal Planned8 topics planned
The circuits connecting chips to reality.
- Current mirrors
- Op-amps
- Bandgap
- LDO
- PLL
- ADC and DAC
- Noise
- Stability
Custom Layout and Memory Planned7 topics planned1 industry project
Standard cells, SRAM and DRAM, down to the layout.
- Standard cells
- Layout
- DRC and LVS
- Parasitic extraction
- 6T SRAM
- DRAM cell and refresh
- Sense amplifiers
Logic Synthesis and STA Planned7 topics planned
How RTL becomes gates that meet timing.
- Synthesis flow
- Liberty libraries
- Constraints
- Timing paths
- OCV
- Multi-corner analysis
- Timing closure
Verification Planned8 topics planned1 major project1 industry project
Find every bug before silicon does.
- SV testbenches
- Randomization
- Coverage
- Assertions
- Scoreboards
- UVM
- Formal
- Regression
Design for Test Planned6 topics planned1 major project
Make every manufactured chip testable.
- Fault models
- Scan
- ATPG
- Compression
- MBIST
- Boundary scan and JTAG
Physical Design Planned9 topics planned1 industry project
RTL to GDS: floorplan through signoff.
- Floorplanning
- Power planning
- Placement
- Clock tree synthesis
- Routing
- ECO
- IR drop and EM
- Signoff
- Tapeout
Post-Silicon Validation Planned7 topics planned1 major project
The day the chip comes back from the fab.
- Bring-up
- ATE
- Characterization
- Shmoo plots
- Silicon debug
- Yield
- Failure analysis
FPGA Planned6 topics planned1 major project
Run your own hardware this week.
- FPGA architecture
- Tool flow
- Constraints
- Timing
- Board bring-up
- Projects
Protocols Library Planned15 topics planned
Every major interface, animated.
- APB
- AHB
- AXI
- UART
- SPI
- I2C
- I3C
- USB
- PCIe
- CXL
- Ethernet
- DDR
- HBM
- UCIe
- MIPI
Computer Architecture and AI Hardware Planned6 topics planned
CPUs, GPUs and accelerators from the inside.
- RISC-V
- Pipelines
- Caches
- GPU architecture
- Accelerators
- Interconnect
Fabrication, Packaging and Careers Planned7 topics planned
How the industry works and how to join it.
- Fab process steps
- Lithography
- Chiplets and packaging
- Companies
- AI data centres
- Resume and portfolio
- Interview bank