Bug Hunt
Every design here is broken on purpose. Read what goes wrong, pick one, and find the line. Each comes with a hint, the fix and why it failed.
2Combinational building blocks5 bugs
MultiplexersWith s = 0 the output shows d[1], and with s = 1 it shows d[0].Decoders and priority encodersA single request gives the right code, but valid stays low unless all four inputs request at once.Half, full and ripple adders3 + 1 gives 0 with no carry out, but 1 + 1 gives 2. Some additions are right and some are badly wrong.Subtractors, comparators and an ALU5 - 5 gives the right result of 0, but the carry flag is 0 when it should be 1. The flag is inverted for every subtraction.Barrel shifters and glitchesPositive numbers divide correctly, but -8 shifted right by 1 gives 124 instead of -4.
3Verilog that means hardware6 bugs
wire, reg, logic and 4-state values5 < 9 works, but -1 < 1 reports false.assign and always blocksIn simulation y ignores changes on b until a changes. The synthesized gates would respond to b straight away.Blocking and non-blocking assignmentsThis should delay d by two clocks, but q2 changes just one clock after d.Accidental latchesAfter s moves from 00 to 10, y keeps its old value instead of going to 0. Synthesis also reports an inferred latch.Parameters and generateLow additions are right, but the top bit of s stays stuck at x, and cout is x too.Your first self-checking testbenchThis check is meant to catch a design whose output isn't 1. The design outputs x, and the check stays silent.
4Sequential logic5 bugs
The D flip-flopThe output changes on the falling clock edge, half a cycle later than the rest of the design expects.Synchronous and asynchronous resetsThis flop should reset at once, even with no clock running. It clears only at the next clock edge.Enables and clock gatingWhen en goes low, q should hold its value. Instead q drops to 0.Shift registersOnly the lowest bit ever changes. The upper bits never pick up any data.LFSRsAfter reset the output is 0 and never changes. It should step through 15 values.
5Counters and frequency dividers5 bugs
Up, down and loadable countersA mod-10 counter should show 0 to 9. This one reaches 10 and then wraps, giving 11 states.Ring, Johnson and Gray countersFrom reset, this Johnson counter stays at 0000 forever. It should go through eight states.Divide by 2, 4 and any even numberThis should divide by 6, but the output toggles every 4 clocks, which divides by 8.Odd division with 50% duty cycleThe output runs at one third of the input frequency, but it is high for 2 of every 3 cycles, not 1.5.Edge detectors and pulse generators
rise should be a one-cycle pulse. It stays high for as long as s is high, apart from the first cycle.6Finite state machines5 bugs
Writing FSMs: encoding and stylebusy goes high in RUN, but it stays high after the machine returns to IDLE.Detecting 1101, with overlapThe stream 1101 is detected, but 11101 is missed, even though it ends in 1101.Non-overlapping detectionThe specification says matches must not share bits, but 1101101 reports two matches rather than one.Traffic light and vending machineCoins of 10 + 10 vend correctly, but 5 + 10 and 5 + 5 + 5 keep the money and vend nothing.Debugging and safe FSMsA bit upset puts the state register at 110. The machine stops there and never leaves, until a reset.
7Memories and FIFOs5 bugs
Register filesThe specification says a read of the address being written returns the new data. This one returns the old value for that cycle.Using SRAM in RTLrd_valid goes high one cycle before the data arrives, so the next block captures stale data.Synchronous FIFOThe FIFO reports full straight after reset, so nothing can ever be written.Valid/ready handshakesWith no stalls everything works. If out_ready goes low, words disappear.Skid buffersThe word caught during a stall is stored but never delivered, and one word is lost each time.
8Arithmetic and datapaths3 bugs
Multipliers and Booth encoding10 x 10 is right, but 100 x 100 gives 16 instead of 10000.Fixed-point arithmetic0.5 x 0.5 is correct, but -0.5 x 0.5 comes out as a large positive number instead of -0.25.PipeliningThe result is right, but valid rises one cycle too early, so the next block captures the wrong value.
10Clock domain crossing5 bugs
The two-flop synchronizerThe signal arrives a cycle sooner than expected, and in silicon this design fails occasionally.Pulse crossing fast to slowOnly every second source pulse produces a destination pulse.Gray code pointersSome consecutive values differ in two bits, so the pointer is unsafe to cross clock domains.Asynchronous FIFOThe FIFO reports full at the wrong times, so data can be overwritten while other flags seem fine.Reset synchronizers and RDCReset releases on the very first clock edge, leaving the first flop no settling time.