Digital Design
Gates to FIFOs, clock crossings and a working CPU. 68 lessons in 12 modules. Pick a module on the left. Videos on the right follow your choice.
Module 1: Numbers and logic
How hardware represents information and decides things.
- 1Binary, hex and two's complementLecture coming soon
- 2Logic gates and truth tablesLecture coming soon
- 3Boolean algebra and De MorganLecture coming soon
- 4Karnaugh mapsLecture coming soon
- 5What a gate is made of: CMOSLecture coming soon
Module 2: Combinational building blocks
Outputs that depend only on the present inputs.
- 6MultiplexersLecture coming soon
- 7Decoders and priority encodersLecture coming soon
- 8Half, full and ripple addersLecture coming soon
- 9Carry look-ahead and prefix addersLecture coming soon
- 10Subtractors, comparators and an ALULecture coming soon
- 11Barrel shifters and glitchesLecture coming soon
Module 3: Verilog that means hardware
Describe circuits, and always picture the circuit you are describing.
- 12Modules, ports and hierarchyLecture coming soon
- 13wire, reg, logic and 4-state valuesLecture coming soon
- 14assign and always blocksLecture coming soon
- 15Blocking and non-blocking assignmentsLecture coming soon
- 16Accidental latchesLecture coming soon
- 17Parameters and generateLecture coming soon
- 18Your first self-checking testbenchLecture coming soon
- 19Reading waveforms like an engineerLecture coming soon
Module 4: Sequential logic
Circuits with memory, and the clock that disciplines them.
- 20SR and D latchesLecture coming soon
- 21The D flip-flopLecture coming soon
- 22Setup and hold: the two promisesLecture coming soon
- 23Synchronous and asynchronous resetsLecture coming soon
- 24Enables and clock gatingLecture coming soon
- 25Shift registersLecture coming soon
- 26LFSRsLecture coming soon
Module 5: Counters and frequency dividers
Timing generators found in nearly every block.
- 27Up, down and loadable countersLecture coming soon
- 28Ring, Johnson and Gray countersLecture coming soon
- 29Divide by 2, 4 and any even numberLecture coming soon
- 30Odd division with 50% duty cycleLecture coming soon
- 31Edge detectors and pulse generatorsLecture coming soon
Module 6: Finite state machines
The control logic behind almost every chip block.
- 32States, transitions and outputsLecture coming soon
- 33Moore and Mealy machinesLecture coming soon
- 34Writing FSMs: encoding and styleLecture coming soon
- 35Detecting 1101, with overlapLecture coming soon
- 36Non-overlapping detectionLecture coming soon
- 37Traffic light and vending machineLecture coming soon
- 38Debugging and safe FSMsLecture coming soon
Module 7: Memories and FIFOs
Moving and storing data between blocks.
- 39Register filesLecture coming soon
- 40Using SRAM in RTLLecture coming soon
- 41Synchronous FIFOLecture coming soon
- 42FIFO depth calculationLecture coming soon
- 43Valid/ready handshakesLecture coming soon
- 44Skid buffersLecture coming soon
Module 8: Arithmetic and datapaths
Making computation fast.
- 45Multipliers and Booth encodingLecture coming soon
- 46Fixed-point arithmeticLecture coming soon
- 47PipeliningLecture coming soon
- 48Retiming and area-speed trade-offsLecture coming soon
Module 9: Static timing
Why a chip has a maximum frequency.
- 49The timing pathLecture coming soon
- 50Clock skew and jitterLecture coming soon
- 51Fixing violationsLecture coming soon
- 52Constraints, false and multicycle pathsLecture coming soon
Module 10: Clock domain crossing
Safely crossing between unrelated clocks.
- 53Metastability and MTBFLecture coming soon
- 54The two-flop synchronizerLecture coming soon
- 55Pulse crossing fast to slowLecture coming soon
- 56Multi-bit transfers and handshakesLecture coming soon
- 57Gray code pointersLecture coming soon
- 58Asynchronous FIFOLecture coming soon
- 59Reset synchronizers and RDCLecture coming soon
Module 11: Designing for silicon
RTL that survives synthesis, lint and power reviews.
- 60What synthesis does to your codeLecture coming soon
- 61Lint and code qualityLecture coming soon
- 62Low-power RTLLecture coming soon
- 63ArbitersLecture coming soon
Module 12: Projects and interview preparation
Bring it all together, and prepare to be hired.
- 64Minor project: UART transmitter and receiverLecture coming soon
- 65Minor project: SPI controllerLecture coming soon
- 66Major project: small RISC-style CPULecture coming soon
- 67Industry project: streaming packet engineLecture coming soon
- 68Interview patternsLecture coming soon
