Digital Design / Module 4: Sequential logic
22. Setup and hold: the two promises
Learn the rule behind all digital timing.
Lab: Setup and hold lab
The idea
A flop makes two demands of its data, and all of digital timing rests on them:
- Setup time: the data must be stable for a short time before the clock edge.
- Hold time: the data must stay stable for a short time after the edge.
Why these exist
The master needs a little time to take in the new value before it closes, which gives setup time. Closing takes a moment too, and a change arriving during that moment could get in, which gives hold time. The values come from the library data for each cell. Hold can even be negative, which means the data may change slightly before the edge.
What happens if you break them
The flop might capture the old value, or the new one, or enter a state, where the internal node sits between 0 and 1 for an unpredictable time. The crossing module looks at this in detail.
Two different problems
A setup violation means the logic is too slow for the clock. Slow down the clock, and it goes away. A hold violation means data arrives too quickly, racing through to the next flop and corrupting the capture. It compares launch and capture at the same edge, so the clock period doesn't appear in the check. The exception is a half-cycle path between a rising-edge flop and a falling-edge flop, where the period does matter.
| Setup | Hold | |
|---|---|---|
| Problem | Data arrives too late | Data changes too soon |
| Depends on clock period | Yes | No |
| Typical fix | Faster logic, slower clock | Add delay to the data path |
Common mistake
Assuming hold can be repaired after manufacture by running the chip more slowly. It can't, which is what makes hold violations so dangerous: such a chip fails at every frequency. Use the lab above to move the data transition around the edge and see each violation.
Key ideas
- Setup: data is stable before the edge.
- Hold: data stays stable after the edge.
- Breaking either can make the flop metastable.
Your exercise
Interview questions
coreCan hold be fixed by slowing the clock?
No, hold doesn't depend on the clock period; add delay in the data path instead.
basicDefine setup time and hold time for a flop.
Setup time is how long the data must be stable before the active clock edge. Hold time is how long it must stay stable after that edge. Together they define a small window around the edge in which the data must not change.
basicWhat can a flop do if its data changes inside the setup-hold window?
It might capture the old value, it might capture the new value, or it might go metastable, with its internal node sitting between 0 and 1 for an unpredictable time before resolving. You cannot rely on which one happens. Metastability is the dangerous case, because the output may resolve late and different downstream flops may read it differently.
coreA path has clock-to-Q of 0.2 ns, worst-case logic delay of 1.5 ns and a capture flop setup time of 0.1 ns, with no clock skew. What is the shortest clock period and the highest frequency?
The data must arrive one setup time before the next edge, so the period must be at least 0.2 + 1.5 + 0.1 = 1.8 ns. The highest frequency is 1 / 1.8 ns, about 555.6 MHz. Any slower clock simply gives more slack on this path.
coreOn a path between two flops, the shortest clock-to-Q is 0.10 ns and the shortest logic delay is 0.05 ns. The capture flop's hold time is 0.08 ns, and its clock arrives 0.10 ns later than the launch flop's. Is hold met, and what is the fix if not?
The new data reaches the capture flop 0.10 + 0.05 = 0.15 ns after the launch edge. It must not arrive before the capture clock time plus hold, which is 0.10 + 0.08 = 0.18 ns. The slack is 0.15 - 0.18 = -0.03 ns, so hold is violated. Add at least 0.03 ns of delay in the data path, usually with buffers; changing the clock period would not help.
coreWhere do setup and hold time come from inside a master-slave flop?
The master latch needs a little time to take in a new value before it closes at the edge, which gives the setup time. Closing is not instant either, and a change that arrives while it is closing can still get in and disturb the captured value, which gives the hold time. The exact numbers come from the cell library's characterisation for each flop.
coreA library flop lists a hold time of -0.02 ns. What does a negative hold time mean, and does it make hold violations impossible?
It means the data may change up to 0.02 ns before the clock edge at the pin and still be captured correctly, typically because the data's path inside the cell is longer than the clock's, so a change at the pin reaches the storage node only after it has closed. It makes hold easier to meet but does not rule out violations: clock skew can make the capture clock arrive later than the launch clock, and the data path can be very short, so the check must still be done.
advancedData is launched by a rising-edge flop and captured by a falling-edge flop. The clock period is 4 ns with a 50% duty cycle, clock-to-Q is 0.2 ns and setup is 0.1 ns. What is the longest allowed logic delay, and how does this path's hold check differ from a normal full-cycle path?
The capture edge is the falling edge 2 ns after the launch, so logic must be at most 2.0 - 0.2 - 0.1 = 1.7 ns. For hold, the relevant capture edge is the falling edge half a cycle before the launch, so the data has an extra half period of margin and hold is easy. This is the case where the clock period, and the duty cycle, do enter the hold relationship, unlike a normal same-edge path.
advancedTo fix a setup violation, someone proposes delaying the clock to the capture flop by 0.3 ns. What does this do to that path's setup and hold, and what else should you check?
It gives the data 0.3 ns more time before the capture edge, so setup slack improves by 0.3 ns. Hold slack on the same path gets 0.3 ns worse, because the capture flop now also samples 0.3 ns later relative to new data. That flop is also a launch flop for the next path, which now starts 0.3 ns late and loses 0.3 ns of setup, so both neighbours must be rechecked.