Digital Design / Module 4: Sequential logic
25. Shift registers
Move and convert serial and parallel data.
See it move
The idea
Chain flops so that each one's output feeds the next. On each clock, every bit moves along one position. It's simple, and it is used everywhere.
always_ff @(posedge clk)
sr <= {sr[N-2:0], din};Because the update is non-blocking, all the flops capture their old neighbour's value at the same instant, which gives a clean shift.
Common uses
- Delay line: N stages delay a signal by N clocks, often used to align a control signal with a pipelined data path.
- Serial in, parallel out (SIPO): shift in N bits, then read the whole word. A receiver works this way.
- Parallel in, serial out (PISO): load a word, then shift it out one bit at a time. A transmitter works this way.
- Pattern matching: compare the last N bits against a constant.
A parameterised SIPO
module sipo #(parameter N = 8) (
input clk, rst, din, en,
output reg [N-1:0] q
);
always_ff @(posedge clk)
if (rst) q <= '0;
else if (en) q <= {q[N-2:0], din};
endmoduleThe first bit in ends up at the top, so this shifts MSB first. A UART sends LSB first, so it would shift the other way: q <= {din, q[N-1:1]};
Hold timing
Shift registers have almost no logic between flops, so they are the classic location for hold problems. Clock between neighbouring flops can let data race through two stages at once. Physical design tools insert delay buffers to fix this.
Common mistake
Using = in the shift. As covered in the blocking lesson, this turns the whole chain into one flop in simulation, or sends the data through in a single clock.
Key ideas
- Chain flops to delay by N cycles.
- SIPO and PISO bridge serial links and parallel buses.
- Non-blocking assignments keep ordering correct.
Your exercise
Find the bug
This code has one deliberate bug. Read the symptom, then click the line you think is wrong.
The fix
if (en) q <= {q[N-2:0], din};Why it failed
{q[N-1:1], din} keeps every upper bit where it already is, and just replaces bit 0. To shift, each bit must take its lower neighbour's value, so the upper part of the new value has to be q[N-2:0].
Interview questions
coreHow would you delay a signal by 8 cycles?
An 8-stage shift register.
basicWhat are serial-in parallel-out and parallel-in serial-out shift registers used for?
A SIPO collects bits arriving one per clock and presents them as a whole word, which is how a serial receiver builds a byte. A PISO loads a whole word at once and sends it out one bit per clock, which is how a serial transmitter works. Together they bridge serial links and parallel buses.
basicThis register starts at 0 and the bits of 8'hA5 are shifted in MSB first, one per clock. What is q after four clocks?
always @(posedge clk)
q <= {q[6:0], din};8'hA5 is 1010_0101, so the first four bits in are 1, 0, 1, 0. Each new bit enters at bit 0 and pushes the older ones up, so after four clocks q is 0000_1010, which is 8'h0A. After all eight, q would be 8'hA5, with the first bit at the top.
coreThis three-stage shift register uses blocking assignments. After one clock with din = 1, what are q1, q2 and q3, and why is that wrong?
always @(posedge clk) begin q1 = din; q2 = q1; q3 = q2; end
All three become 1 after one clock. Each line reads the value written by the line above in the same pass, so din runs through the whole chain in a single edge and the register behaves like one flop. With non-blocking assignments every stage reads its neighbour's old value, giving 1, 0, 0 as intended.
coreThis PISO is loaded with 8'hC1 and then shifts. Which bit order appears on tx, and how would you change it to send MSB first?
always @(posedge clk)
if (load) p <= data;
else p <= {1'b0, p[7:1]};
assign tx = p[0];tx is p[0], and the register shifts right, so bits leave LSB first. For 8'hC1, which is 1100_0001, the order on tx is 1, 0, 0, 0, 0, 0, 1, 1. For MSB first, take tx from p[7] and shift left with p <= {p[6:0], 1'b0}.
coreWhy are shift registers a classic place for hold violations, and how are they normally fixed?
There is almost no logic between neighbouring flops, so the data path is just clock-to-Q plus a wire. If the capture flop's clock arrives a little later than the launch flop's, the new data can arrive before the hold window has closed and race through two stages in one edge. Physical design tools fix this by inserting delay buffers in the data path; slowing the clock would not help.
coreA control signal must stay aligned with data passing through a 4-stage pipeline. How do you do this, and what goes wrong if you get the count wrong?
Pass the control signal through a 4-stage shift register, one flop per pipeline stage, so it reaches the end on the same cycle as its data. If you use one stage too few or too many, the control arrives a cycle early or late and acts on the neighbouring data item. This kind of off-by-one is easy to spot on a waveform by comparing the control with the data it should accompany.
advancedYou need to delay an 8-bit data stream by 1,000 cycles. Would you build 8,000 flops? What are the alternatives?
A chain of 1,000 x 8 = 8,000 flops works but is expensive in area and clock power. A common alternative is a 1,000-entry memory used as a circular buffer: each cycle, read the oldest sample at the pointer, write the new sample in its place and advance the pointer, adjusting the depth for the memory's read latency. If the signal is a rare single-bit pulse instead of a stream, a counter that starts on the pulse and fires after 1,000 cycles is far smaller, provided pulses never overlap.
advancedTo detect the pattern 1101 in a serial stream, a designer keeps the last four bits in a shift register and compares them with 4'b1101. How does this compare with a state machine, including overlapping matches?
The shift register sees the last four bits directly, so the compare finds every match, including overlapping ones, with no extra effort. It always needs as many flops as the pattern has bits, and the match is known once the last bit has been shifted in. A state machine records only how much of the pattern matched so far, which can need fewer flops for long patterns, but its transitions must be designed carefully to handle overlap. For short patterns the shift register is often the simpler and safer choice.