Lab: Timing path lab
The idea
A chip's maximum frequency is set by its slowest path between flops. A signal leaves one flop at a clock edge, travels through logic, and must arrive at the next flop before the following edge. Static timing analysis (STA) checks every such path, without running any test vectors.
The setup check
All of these must fit within one clock period:
Tclk >= Tcq + Tcomb + Tsetup
Slack is the margin left over. Positive means the path passes, and negative means it fails.
Setup slack = Tclk - (Tcq + Tcomb + Tsetup)
Worked example
Given Tcq = 0.3 ns, Tcomb = 2.2 ns, and Tsetup = 0.5 ns:
- The minimum period is 0.3 + 2.2 + 0.5 = 3.0 ns.
- So fmax = 1 / 3.0 ns, which is about 333 MHz.
- At a 3.5 ns clock, the slack is +0.5 ns. At 2.8 ns, it is -0.2 ns, a violation.
The hold check
New data launched at an edge must not reach the capture flop too soon, or it would corrupt the value being captured by that same edge.
Tcq + Tcomb >= Thold
The clock period isn't in this equation. With no logic between flops and a large , this can fail at any frequency.
Why STA instead of simulation
Simulation only checks the paths your tests exercise. STA examines all paths structurally, using the worst and best-case cell delays. On a chip with millions of flops, no realistic test set could do this. The trade-off is that STA doesn't know which paths can actually occur, so you must tell it about exceptions. The Constraints lesson covers this.
Common mistake
Using one set of delays for both checks. Setup is checked with the slowest conditions on the data path, and hold with the fastest. Real tools run many corners, covering process, voltage and temperature combinations. Move the sliders in the lab above to see both slack values respond.
Key ideas
- Tclk >= Tcq + Tcomb + Tsetup (ideal clock).
- Hold: Tcq + Tcomb >= Thold.
- Slack is required time minus arrival time.
Your exercise
Interview questions
coreWhat's the fmax for that path?
1/3 ns, about 333 MHz.
basicWhat is setup slack, and what does its sign tell you?
Setup slack is the required time minus the arrival time. The required time is the next clock edge minus the setup time, and the arrival time is clock-to-Q plus the logic delay. Positive slack means the data arrives with time to spare, so the path passes. Negative slack means the data arrives too late, so the path fails at that clock period.
basicTcq = 0.2 ns, Tcomb = 1.5 ns, Tsetup = 0.1 ns, and the clock period is 2.0 ns. What is the setup slack, and what is fmax for this path?
Arrival is 0.2 + 1.5 = 1.7 ns. Required is 2.0 - 0.1 = 1.9 ns. Slack is 1.9 - 1.7 = +0.2 ns, so the path passes. The minimum period is 0.2 + 1.5 + 0.1 = 1.8 ns, so fmax = 1 / 1.8 ns, about 555.6 MHz.
coreTwo flops are joined by a short wire: Tcq = 0.1 ns, Tcomb = 0.05 ns and Thold = 0.2 ns. Does the path meet hold? What happens if you lower the clock frequency?
Hold requires Tcq + Tcomb >= Thold. Here 0.1 + 0.05 = 0.15 ns, which is less than 0.2 ns, so the hold slack is -0.05 ns, a violation. Lowering the frequency does nothing, because the clock period doesn't appear in the hold check. The fix is to add delay to the data path, for example a buffer of at least 0.05 ns.
coreWhy does the clock period appear in the setup check but not in the hold check?
Setup compares data launched at one edge with the capture at the next edge, so the time between them, the period, is the budget. Hold compares data launched at an edge with the capture at that same edge: the new data must not arrive so soon that it corrupts the value being captured. Both events follow the same edge, so the period cancels out.
coreA capture flop is fed by two paths from the same launch flop: one with 2.4 ns of logic and one with 0.05 ns. Tcq = 0.3 ns, Tsetup = 0.5 ns, Thold = 0.4 ns, and the period is 3.5 ns. Which path decides each check, and do they pass?
Setup is decided by the slowest path: 3.5 - (0.3 + 2.4 + 0.5) = +0.3 ns, a pass. Hold is decided by the fastest path: 0.3 + 0.05 - 0.4 = -0.05 ns, a fail. The same endpoint can pass setup and fail hold, because the two checks look at opposite extremes of the paths reaching it.
coreWhy do chip teams rely on static timing analysis instead of timing simulation to sign off timing?
Simulation only exercises the paths that the test vectors happen to activate, and it would need huge numbers of vectors on a big chip. STA checks every path structurally, using worst-case and best-case delays, without any vectors, so it is complete and fast. The cost is that STA doesn't know which paths can really occur, so the designer must declare false paths and multicycle paths.
advancedAt the slow corner, Tcq = 0.4 ns, Tcomb = 2.6 ns and Tsetup = 0.6 ns. At the fast corner, Tcq = 0.15 ns, Tcomb = 0.1 ns and Thold = 0.3 ns. What is fmax, and does hold pass?
Setup uses the slow corner: 0.4 + 2.6 + 0.6 = 3.6 ns, so fmax = 1 / 3.6 ns, about 277.8 MHz. Hold uses the fast corner: 0.15 + 0.1 - 0.3 = -0.05 ns, so hold fails. Checking hold with slow-corner delays would hide it. Real flows check many process, voltage and temperature corners for this reason.
advancedA path is launched on the rising edge and captured on the falling edge of a 4 ns clock. Tcq = 0.3 ns, Tcomb = 1.4 ns and Tsetup = 0.4 ns. Does it meet setup?
No. From a rising edge to the next falling edge is only half a period, 2.0 ns. The path needs 0.3 + 1.4 + 0.4 = 2.1 ns, so the slack is -0.1 ns. A rising-to-rising path would have 4.0 ns and pass with +1.9 ns. Hold, on the other hand, gets an extra half period of margin, because the hold check is against the falling edge half a period before the launch edge.