Lab: Timing path lab
The idea
When a timing report shows violations, the fix depends on the type. Setup violations are about being slow, and hold violations are about being fast, so their fixes are opposites.
Fixing setup violations
Try these roughly in this order:
- Check the constraint. Is this a , or a path, that was not declared? Don't fix what isn't real.
- Restructure the logic. Put late-arriving signals closer to the output. Replace long priority chains with flatter logic.
- Add a stage. Very effective, but it changes , so you must alter the design.
- Upsize cells. Let the tool use larger drive strengths and low-threshold cells, at some area and leakage cost.
- Reduce load. Duplicate high-fanout logic, and buffer long wires.
- Lower the frequency. The last resort, usually a product decision.
Fixing hold violations
Hold is simple in principle: add delay on the data path, typically with buffers. The tool does this late in the flow, once the clock tree exists and real is known. Fixing hold too early wastes effort, because the numbers will change. Be careful, though: that delay must not break setup on the same path.
Why hold is more dangerous
| Setup failure | Hold failure | |
|---|---|---|
| After fabrication | Run the clock more slowly | No frequency helps |
| Severity | Chip works, more slowly | Chip may be scrap |
Reading a report
A timing report lists a path's start point, end point, each cell's delay, and the final . Look first for what's unusual: a cell driving a huge load, a long wire, or a path crossing many hierarchy levels. Fix the worst path, then rerun. Often a single fix helps many paths that share logic.
Common mistake
Attempting to close timing purely with tool options when the logic depth is simply too great. If a path has 40 levels of logic at a clock that allows 15, no optimisation can save it. Change the RTL.
Key ideas
- Setup: pipeline, restructure, or upsize.
- Hold: add buffers on the data path.
- Setup depends on frequency; hold doesn't.
Your exercise
Interview questions
coreWhy are hold violations serious?
No clock speed fixes them after fabrication.
basicWhy do setup and hold violations need opposite fixes?
A setup violation means data arrives too late for the next edge, so the path must become faster, for example with less logic, bigger cells or a pipeline stage. A hold violation means data arrives too soon after the same edge, so the path must become slower, usually by adding buffers. A change that helps one usually costs margin on the other, so check both after any fix.
basicA timing report shows a large setup violation on a path. What should you check before changing any logic?
Check that the constraint is real. The path may be a false path, for example between unrelated clocks or through a static configuration register, or a multicycle path that was not declared. Fixing a path that never needs to meet single-cycle timing wastes area and effort. Only once the requirement is confirmed should you restructure, pipeline or upsize.
coreA three-gate AND chain has one input that arrives late, at 1.0 ns. The others arrive at 0.3 ns, and each gate takes 0.2 ns. Which ordering is faster, and by how much?
`timescale 1ns/1ps module chain(input a, b, c, late, output y_first, y_last); wire n1, n2, m1, m2; and #0.2 g1(n1, late, a), g2(n2, n1, b), g3(y_first, n2, c); and #0.2 h1(m1, a, b), h2(m2, m1, c), h3(y_last, m2, late); endmodule
Feeding the late input into the first gate makes it pass through all three gates: 1.0 + 3 x 0.2 = 1.6 ns. Feeding it into the last gate means the early inputs are already combined, ready at 0.3 + 2 x 0.2 = 0.7 ns, so the output settles at 1.0 + 0.2 = 1.2 ns. That saves 0.4 ns with the same logic. A gate-delay simulation of these two modules gave exactly 1.6 ns and 1.2 ns.
coreA path has -0.08 ns hold slack and +0.5 ns setup slack. Each delay buffer adds 0.03 ns. How many buffers do you add, and what are the final slacks?
Three buffers are needed, since two give only 0.06 ns, which is not enough, and three give 0.09 ns. Hold slack becomes -0.08 + 0.09 = +0.01 ns. Setup slack drops by the same 0.09 ns to +0.41 ns, which is still fine. The setup slack must be checked, because the added delay applies to both checks.
coreA single flop drives an enable to 400 flops spread across the block, and that net fails setup. What can you do in RTL or synthesis?
Reduce the load. Duplicate the driving flop so that each copy drives a nearby group, which shortens the wires and divides the fanout. Alternatively, build a buffer tree, which the tool may do itself. Duplicated flops must be kept from being merged back together by optimisation, using the tool's directive for that. If the enable is computed late, also look at moving its logic earlier, or pipelining it by a cycle if the design can accept that.
coreWhy is hold fixing usually left until after clock tree synthesis?
Hold slack depends heavily on clock skew, and before the clock tree exists, skew is only an estimate. Fixing hold early could insert many buffers for violations that disappear once the real tree is built, or miss ones that appear. Setup work is done throughout the flow, but hold is fixed once real clock arrival times are known.
advancedA path has 36 levels of logic at 0.12 ns per level, and the logic budget per cycle is 1.6 ns. How many pipeline stages do you need?
The path takes 36 x 0.12 = 4.32 ns, far more than 1.6 ns, so no cell sizing will save it. Each stage can hold at most floor(1.6 / 0.12) = 13 levels, which is 1.56 ns. So you need ceil(36 / 13) = 3 stages, which means adding two pipeline registers. Balanced as 12 levels each, every stage takes 1.44 ns, leaving some margin.
advancedAfter hold buffers were added at a flop's input, a different path into the same flop started failing setup. What happened, and what is the better fix?
The buffers were placed at the endpoint, where both the short path and the long path converge, so they delayed both. The short path needed delay, but the long path had little setup margin to give. The better fix is to insert the delay only on the short branch, before it joins the long one. If both paths are tight, the window between setup and hold is too small, and the logic or the clocking has to change.