See it move
The idea
Power limits most modern chips, from phones to data centres. To lower it, you need to know where it goes.
Two kinds of power
Dynamic power is used when signals switch: P = α · C · V² · f
αis the activity, or how often nodes switch.Cis the capacitance switched.Vis the supply voltage, and it's squared.fis the clock frequency.
Static power is leakage, which flows even when nothing switches. It depends on temperature and on transistor type.
RTL techniques
- : this is the most common technique, since clocks often take a large share of dynamic power. Stop the clock when a register doesn't need to update.
- Operand isolation: hold a multiplier's inputs steady when its result isn't needed, so that it doesn't switch for no reason.
- Avoid needless activity: don't update registers with values that are never used. Encodings like Gray, or , can reduce toggling on specific buses.
- Use memory carefully: access only when needed, keep chip-select low, and use smaller or banked memories.
System techniques
- Voltage islands: run each block at the lowest voltage it can.
- Dynamic voltage and frequency scaling: lower both when demand is low. As P depends on V squared, this saves a lot.
- Power gating: cut the supply from idle blocks to stop leakage, using retention flops and isolation cells at the boundaries.
Worked example
With α = 0.15, C = 10 pF, V = 0.8 V and f = 1 GHz, P = 0.15 x 10 pF x 0.64 x 1 GHz = 0.96 mW. Drop the voltage by 10%, and P falls by about 19%. Halve the activity, and P falls by 50%.
Common mistake
Forgetting that voltage and frequency are linked. You can't lower the voltage freely, since gates get slower, and timing must still close. Check any power saving against the timing budget. Also, savings claimed before layout are only estimates, so measure them with real activity data.
Key ideas
- Dynamic power: activity, capacitance, voltage squared, frequency.
- Gate clocks of idle blocks.
- Operand isolation stops needless toggling; voltage islands and power gating come next.
Your exercise
Find the bug
This code has one deliberate bug. Read the symptom, then click the line you think is wrong.
The fix
reg en_lat = 1'b0; always @(*) if (!clk) en_lat = en; assign gclk = clk & en_lat;
Why it failed
When the clock is high, an AND gate passes any change on en straight to its output. The fix holds the enable in a latch that is open only when the clock is low. It then can't change while the clock is high, so every output pulse is whole. Real designs use the library's clock-gating cell for this.
Interview questions
coreMost effective power knob?
Voltage, since dynamic power scales with V^2, subject to timing limits.
basicA block has activity 0.2, switched capacitance 5 pF, supply 0.9 V and a 500 MHz clock. What is its dynamic power?
Dynamic power is alpha x C x V^2 x f. That is 0.2 x 5 pF x 0.81 x 500 MHz. 0.2 x 5 pF = 1 pF, times 0.81 is 0.81 pF, times 500 MHz gives 0.405 mW. Leakage is extra and is not part of this formula.
basicWhat is the difference between dynamic and static power, and which one does clock gating reduce?
Dynamic power is spent when nodes switch, charging and discharging capacitance. Static power is leakage, which flows even when nothing switches, and it depends on temperature and transistor type. Clock gating removes clock edges that would only reload the same value, so it reduces dynamic power. Leakage needs other techniques, such as cutting the supply to idle blocks with power gating.
coreDynamic voltage and frequency scaling lowers both the supply and the clock frequency by 20 percent. How much dynamic power is saved?
Power scales with V^2 x f, so the new power is 0.8^2 x 0.8 = 0.64 x 0.8 = 0.512 of the original. That is a saving of about 49 percent. The voltage term does most of the work because it is squared. The lower frequency is needed because gates are slower at the lower voltage.
coreWhy is this clock gate a problem when en comes from a flop on the rising edge of clk?
always @(posedge clk) en <= en_next; assign gclk = clk & en;
en changes just after the rising edge, while clk is high. If en rises, gclk gets a late rising edge in the middle of the high phase; if en falls, gclk is cut short into a narrow pulse. Either can clock the gated flops at the wrong moment. A proper clock gate holds the enable in a latch that is transparent only while clk is low, so the enable is stable for the whole high phase and gclk is always a complete pulse.
coreA 64-bit register loads one cycle in four. Each flop's clock pin has 1.5 fF, the supply is 0.9 V and the clock is 500 MHz. Estimate the clock-pin power with a plain enable and with clock gating.
With an enable, every clock pin toggles every cycle, so activity is 1: 64 x 1.5 fF x 0.81 x 500 MHz is about 38.9 microwatts. With clock gating, the flops only get an edge when they load, so activity is 0.25 and the power is about 9.7 microwatts, plus the gate's own input. The gate itself still sees every edge, but it is one cell instead of 64 flops. The stored values are identical in both cases.
coreWhat is operand isolation, and when is it not worth it?
Operand isolation holds the inputs of a block steady, for example by gating them to zero, when its result will not be used. A multiplier fed from a busy bus then stops switching internally on cycles where the product is thrown away. It is not worth it when the result is used most cycles, when the block is small, or when the isolation gates would land on a critical timing path. Like any power change, it should be judged with real activity data.
advancedHalving the clock frequency halves dynamic power. Does it also halve the energy needed to finish a fixed task?
No. Dynamic energy per operation is roughly alpha x C x V^2, which does not depend on frequency. At half the frequency, the task takes twice as long, so the dynamic energy for the task stays about the same, and leakage energy actually grows because the chip is on for longer. Real energy savings come from lowering the voltage, which a lower frequency makes possible.
advancedPower gating cuts the supply to an idle block. Why does it need isolation cells and retention flops?
When a block is powered down, its outputs float to unknown levels, and neighbouring blocks that are still powered could read garbage or draw current through partly switched inputs. Isolation cells at the boundary clamp those outputs to known values while the block is off. Retention flops keep the state that must survive, on a small always-on supply, so the block can resume without being reloaded from scratch. Both add area and control sequencing, so power gating pays off mainly for blocks that are idle for long periods.