See it move
The idea
Everything so far has had no memory. Feed a gate's output back to its input, however, and the circuit can hold a value by itself. This is how a bit gets stored.
The SR latch
Cross-couple two NOR gates. Each gate's output feeds the other's input.
| S | R | Result |
|---|---|---|
| 0 | 0 | Hold the value |
| 1 | 0 | Set: Q = 1 |
| 0 | 1 | Reset: Q = 0 |
| 1 | 1 | Forbidden |
With S = R = 0, the loop reinforces whichever value it already has. With S = R = 1, both outputs go low. They are no longer opposites, and if both inputs are released at once, the final value is unpredictable.
The D latch
A D latch removes the forbidden case. It has a data input D and an enable. While enabled it is transparent: Q follows D. While disabled, it holds. It is level-sensitive, so any change on D during the enabled phase passes through.
always_latch begin
if (en) q = d;
endLatches or flops
Most logic uses flops, because they change at one instant, which makes timing easy to reason about. Latches do appear on purpose: in cells, in some memories, and in high-speed designs that use time borrowing. There, a slow path may take a little time from the next stage, as long as the data arrives while the latch is open.
Common mistake
Confusing "latch" and "flop" in an interview. A latch is sensitive to a level, and a flop to an edge. Use the second animation to compare them with the same inputs: the latch output follows every wiggle during the enabled phase, whereas the flop ignores them.
One more to try
Key ideas
- Cross-coupled gates hold state.
- A D latch is transparent while enabled.
- Latches allow time borrowing but complicate timing.
Your exercise
Interview questions
coreLatch or flop: level or edge sensitive?
A latch is level sensitive; a flop is edge triggered.
basicFor an SR latch built from two cross-coupled NOR gates, what happens for each combination of S and R?
With S = 0 and R = 0 the loop holds whatever value it already has. S = 1, R = 0 sets Q to 1, and S = 0, R = 1 resets Q to 0. S = 1, R = 1 is forbidden, because it forces both outputs low so they are no longer opposites, and the value after releasing both is unpredictable.
basicWhat does a D latch do while its enable is high, and while it is low?
While enabled it is transparent: Q follows D, so every change on D passes through to Q. While disabled it holds the value D had when the enable went low. It responds to a level, not an edge, which is the key difference from a flop.
coreIn a NOR SR latch, S and R are both 1. What are Q and Q-bar, and what happens if both inputs drop to 0 at exactly the same time?
Both outputs are 0, since a NOR with any input at 1 outputs 0. When both inputs fall together, each gate sees two zeros and tries to drive 1, which then forces the other back to 0. With perfectly equal gate delays this simply repeats; in simulation with 1 ns per gate, both outputs toggled together every nanosecond. Real gates are never exactly matched, so it settles to one side or the other, and you cannot predict which.
coreAn SR latch is built from two cross-coupled NAND gates instead of NOR. How do its inputs behave, and which input combination is forbidden?
The inputs become active low. With both inputs at 1 the latch holds, pulling the set input low makes Q = 1, and pulling the reset input low makes Q = 0. Both inputs low is forbidden, because a NAND with a 0 input outputs 1, so both outputs go high together.
coreA D latch and a rising-edge flop receive the same D and the same clock, and D wiggles several times while the clock is high. How do the two outputs differ?
The latch is open during the whole high phase, so its output copies every wiggle and then holds the value D had when the clock fell. The flop samples D only at the rising edge and ignores everything after it until the next rising edge. So the latch output shows several changes in that phase, while the flop output changes at most once, at the edge.
coreThis code is meant to model a D latch. In simulation, with en held high, D changes from 0 to 1 but q stays 0. Why?
always @(en) if (en) q = d;
The block only wakes when en changes, because d is missing from the event list. While en stays high, changes on d never run the block, so q misses them, which is not how a transparent latch behaves. Use always @(*) or list both, always @(en or d), so any change on d during the enabled phase reaches q. Synthesis would usually build a real latch anyway, so the simulation and the hardware would disagree.
advancedA design runs on a 10 ns clock with a 50% duty cycle. Stage 1 logic needs 12 ns and stage 2 needs 7 ns. Ignoring setup and latch delays, can it work with flops between the stages? Can it work if the middle element is a latch that is open during the high phase?
With flops, stage 1 must fit in one 10 ns cycle, and 12 ns does not, so it fails. With a latch, the data arrives 2 ns into the latch's open window, passes straight through, and stage 2 starts at 12 ns and finishes at 19 ns, before the next capture at 20 ns. Stage 1 has borrowed 2 ns from stage 2, which works because 2 ns is within the 5 ns open window and the two stages together, 19 ns, fit in two cycles.
advancedA latch's enable is driven by combinational logic that can glitch high for a moment while it is meant to stay low. Why is this a real problem for a latch, when a glitch of the same kind on a flop's D input usually is not?
A latch is open for as long as its enable is high, so even a short glitch on the enable opens it and lets whatever D holds at that moment overwrite the stored value. A glitch on a flop's D input does not matter as long as D has settled by the next sampling edge, because the flop only looks at D around the edge. That is why latch enables and clock-like signals need glitch-free sources.