See it move
The idea
A must absorb the difference between how fast data comes in and how fast it leaves. Too shallow means lost data, and too deep wastes area. The sizing question is common in interviews, and the reasoning is simple: how many words pile up in the worst case?
The basic calculation
During a burst, words arrive at the write rate while some leave at the read rate. Whatever remains is what the FIFO must hold.
depth = burst length - words read during the burst
Worked example
A 100-word burst is written at 100 MHz, and reads run at 50 MHz.
- The burst lasts 100 words / 100 MHz = 1 µs.
- In 1 µs, reads remove 50 MHz x 1 µs = 50 words.
- So the FIFO must hold 100 - 50 = 50 words.
With idle cycles
If the reader takes one word every 4 clocks at 50 MHz, its effective rate is 12.5 MHz, so in 1 µs it removes 12.5 words. Round the words removed down, since a partial word frees no space. That gives 12 words read, and a depth of 100 - 12 = 88 entries.
Add margin
Real designs need more than the ideal number:
- Reads may start late, so data can pile up before the first read.
- An async FIFO's flags are delayed by , which reserves a few entries.
- Pipelined writers may have words in flight after
fullrises.
When no depth can work
If the average write rate exceeds the read rate forever, the FIFO will eventually overflow, whatever its depth. A FIFO absorbs bursts, but it can't fix a sustained mismatch. That needs , or a faster reader.
Common mistake
Assuming the worst case is a single burst. Find out about back-to-back bursts. Two bursts may arrive with too short a gap for the FIFO to drain between them, which increases the required depth. Ask about this in the interview. Use the lab below to try different bursts and clock rates.
Key ideas
- Backlog is what's written minus what's read during a burst.
- Ideal depth = burst length minus the words read while the burst lasts.
- Add margin for synchronizer latency in async FIFOs.
Lab: FIFO depth lab
Your exercise
Interview questions
coreBurst 100 at 100 MHz, reads at 50 MHz?
Burst takes 1 us; 50 are read in that time, so at least 50 entries, plus margin for implementation latency.
basicA writer sends at 100 MHz continuously and the reader takes words at 90 MHz continuously. What FIFO depth do you need?
No depth is enough. The backlog grows by 10 million words per second for as long as the traffic lasts, so any finite FIFO eventually overflows. A FIFO absorbs a temporary difference, such as a burst, but it can't fix a sustained rate mismatch. That needs backpressure to slow the writer, or a faster reader.
basicAn 80-word burst is written at 200 MHz, and the reader runs at 120 MHz, one word per cycle. What is the ideal FIFO depth?
The burst lasts 80 / 200 MHz = 400 ns. In 400 ns the reader removes 120 MHz x 400 ns = 48 words. So the backlog peaks at 80 - 48 = 32 words, and the ideal depth is 32. A real design adds margin on top of that, for example for clock phase and for latency before reading starts.
coreA 120-word burst arrives at 100 MHz. The reader's clock is 80 MHz, but it takes a word only every second cycle. What depth do you need?
The reader's effective rate is 80 / 2 = 40 MHz. The burst lasts 120 / 100 MHz = 1.2 us, so the reader removes 40 MHz x 1.2 us = 48 words. The FIFO must hold 120 - 48 = 72 words, plus margin. The common trap is to use the 80 MHz clock rate instead of the rate at which words actually leave.
coreA 50-word burst arrives at 100 MHz, and the reader runs at 33 MHz. What depth do you choose, and which way do you round?
The burst lasts 50 / 100 MHz = 500 ns. The reader removes 33 MHz x 500 ns = 16.5 words. Round the words read down to 16, because half a word read frees no space, which gives 50 - 16 = 34. Rounding up to 17 would give 33, which can be one too small. Rounding toward the larger depth is the safe direction.
coreA 100-word burst arrives at 100 MHz, and the 50 MHz reader starts 200 ns after the burst begins. What depth do you need?
The burst lasts 100 / 100 MHz = 1 us, but the reader is active for only the last 800 ns of it. In that time it removes 50 MHz x 0.8 us = 40 words. So the FIFO must hold 100 - 40 = 60 words, compared with 50 if the reader started at once. Read start-up delay is one of the most common reasons real FIFOs need more than the ideal figure.
coreYour calculation says a depth of 50 is enough, but a cycle-accurate simulation shows the FIFO peaking at 51 entries. Is the simulation wrong?
Probably not. The formula treats reads as a smooth rate, but real reads happen on discrete clock edges. Depending on how the reader's edges line up with the first write, the reader may lose its first chance because the FIFO is still empty. That leaves one extra word inside at the peak. This is one reason to add margin, and to check the peak in simulation with different starting phases.
advancedTwo 100-word bursts arrive at 100 MHz with a 60-cycle (600 ns) gap between them, and the reader runs at 50 MHz. What depth is needed, and how long must the gap be for one burst's depth to be enough?
After the first burst (1 us), 100 - 50 = 50 words remain. During the 600 ns gap, the reader removes 50 MHz x 0.6 us = 30 words, leaving 20. The second burst then adds another net 50, so the peak is 20 + 50 = 70. For the depth of a single burst (50) to suffice, the gap must let the reader drain all 50 words: 50 / 50 MHz = 1 us, or 100 cycles at 100 MHz.
advancedA writer at 100 MHz sends 80 words in every 100-cycle frame, placed anywhere in the frame. The reader takes one word every cycle at 80 MHz. What is the ideal depth?
The worst case is 80 words at the end of one frame followed by 80 at the start of the next: 160 words back-to-back. That takes 160 / 100 MHz = 1.6 us, during which the reader removes 80 MHz x 1.6 us = 128 words. So the ideal depth is 160 - 128 = 32. The average rates match (80 million words per second each), so the backlog doesn't grow from frame to frame, and the double burst is the worst case. A larger answer comes from not finding the worst arrangement, and a smaller one from using a single frame.