Digital Design / Module 1: Numbers and logic
5. What a gate is made of: CMOS
See the transistors and the delay behind every symbol.
See it move
The idea
A gate symbol hides a pair of switch networks. A transistor acts as a voltage-controlled switch. An NMOS conducts when its gate is high and is good at pulling a node down to 0. A PMOS conducts when its gate is low and is good at pulling a node up to 1.
Complementary networks
Every static CMOS gate has a PMOS network between the supply and the output, plus an NMOS network between the output and ground. They are built so that exactly one conducts for any stable input.
In a 2-input NAND, the NMOS devices are in series, so the output falls only if both inputs are high. The PMOS devices are in parallel, so either low input pulls the output high. A NOR swaps these: series PMOS and parallel NMOS. Notice that a single CMOS stage always inverts. That is why NAND is more basic than AND, which needs an extra inverter.
Where delay comes from
The output drives a load capacitance, made up of the next gates' inputs and the wires. Switching means charging or discharging that capacitance through transistors, which behave like resistors. More load means more delay, and a wider transistor gives more drive at the cost of area and input capacitance.
Where power goes
Dynamic power is P = α · C · V² · f, where α is how often the node switches. Voltage has the strongest effect because it is squared. Leakage still flows when nothing switches, and it matters a great deal in modern processes.
Why NAND is usually preferred to NOR
Series transistors are slow, and PMOS carries less current than NMOS of the same size. A NOR places its PMOS devices in series, the worst combination, so they must be made wider to compensate. A NAND places the faster NMOS devices in series instead, so it is normally the better choice.
Common mistake
Believing CMOS uses no power when idle. Ideally, one network is off in each steady state. In practice leakage flows through devices that are "off", and it can take up a large share of a chip's total power.
Key ideas
- PMOS pulls up and NMOS pulls down, in complementary networks.
- Delay comes from charging and discharging load capacitance.
- Dynamic power follows activity x C x V^2 x f.
Your exercise
Interview questions
coreWhy is static CMOS low in static power?
Ideally one network is off in each steady state, so only leakage flows.
basicHow many transistors are in a static CMOS inverter, a 2-input NAND and a 2-input AND?
An inverter has 2, one PMOS and one NMOS. A 2-input NAND has 4, two of each. A 2-input AND is a NAND followed by an inverter, so it has 6. Since a single CMOS stage always inverts, the non-inverting gate is the bigger one.
basicIn a 2-input CMOS NAND with A = 1 and B = 0, which transistors conduct, and what is the output?
The NMOS devices are in series, and the one driven by B is off, so there is no path to ground. The PMOS devices are in parallel, and the one driven by B is on because its gate is low, so the output is pulled to 1. The PMOS on A and the NMOS on B are off; the NMOS on A is on but cannot complete the path alone.
coreSupply voltage drops from 1.0 V to 0.8 V with frequency and activity unchanged. By how much does dynamic power fall?
Dynamic power scales with V squared, so it becomes 0.8^2 = 0.64 of its old value, a 36 percent reduction. A 20 percent voltage cut gives a much larger power saving because of the square. In practice, a lower supply also slows the gates, so frequency often has to drop as well.
coreA block switches a total of 1 nF of capacitance with activity factor 0.1, at 0.9 V and 500 MHz. Estimate its dynamic power with P = α·C·V²·f.
P = 0.1 × 1e-9 F × 0.81 V² × 5e8 Hz = 0.0405 W, about 40 mW. The 0.81 comes from squaring 0.9 V. Some texts put a factor of one half in this formula, depending on how α is defined, so an interviewer may expect that variant; what matters is using one definition consistently.
coreWhy can't a single static CMOS stage implement a non-inverting function such as AND?
An NMOS turns on when its input rises, and it sits in the pull-down network, so rising inputs can only pull the output down. A PMOS turns on when its input falls, and it sits in the pull-up network. Either way, an input moving one way pushes the output the other way. A non-inverting function therefore needs a second stage, usually an inverter.
coreDescribe the transistor networks of a 3-input NOR, and explain why it is a poor choice compared with a 3-input NAND.
The NOR has three PMOS in series between the supply and the output, and three NMOS in parallel to ground. Series transistors add resistance, and PMOS already carries less current than an NMOS of the same size, so the pull-up is slow and the PMOS must be made much wider. A NAND puts the stronger NMOS in series instead, so it gets the same speed in less area.
advancedDesign a single static CMOS stage for F = (AB + C)'. How many transistors does it need?
Build the pull-down from the uninverted expression: NMOS A and B in series, with NMOS C in parallel with that pair. The pull-up is the dual: PMOS A and B in parallel, in series with PMOS C. That is 6 transistors in one inverting stage, fewer than a separate AND, OR and inverter. Gates like this are called AND-OR-invert cells.
advancedIf you halve the clock frequency of a block, does the dynamic energy per operation go down?
Not by itself. Each transition still charges the same capacitance to the same voltage, so dynamic energy per operation is about the same; only power halves, because operations happen half as often. Leakage energy per operation actually rises, since each operation now takes longer. Real energy savings come from lowering voltage, reducing activity, or switching less capacitance.